Code_ The Hidden Language of Computer Hardware and Software - Charles Petzold [123]
Eight-bit microprocessors such as the 8080 and 6800 have 16-bit addresses that can address a total of 64 KB of memory. When you wire a 4-KB memory board containing four banks of chips, the memory board's 16 address signals perform the following functions:
The 10 address signals A0 through A9 are directly wired to the RAM chips. The address signals A10 and A11 select which of the four banks is being addressed. The address signals A12 through A15 determine which addresses apply to this particular board—in other words, the addresses that the board responds to. The 4-KB memory board we're designing can occupy one of 16 different 4-KB ranges in the entire 64-KB memory space of the microprocessor:
0000h through 0FFFh, or
1000h through 1FFFh, or
2000h through 2FFFh, or
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F000h through FFFFh.
For example, suppose we decide that this 4-KB memory board will apply to addresses A000h through AFFFh. This means that addresses A000h through A3FFh will apply to the first bank of 1-KB chips, addresses A400h through A7FFh to the second bank, addresses A800h through ABFFh to the third bank, and addresses AC00h through AFFFh to the fourth bank.
It's common to wire a 4-KB memory board so that you can flexibly specify at a later time what range of addresses it responds to. To achieve this flexibility, you use something called a DIP switch. This is a series of tiny switches (anywhere from 2 through 12) in a dual inline package (DIP) that can be inserted in a normal IC socket:
You can wire this switch with the high 4 address bits from the bus in a circuit called a comparator.
As you'll recall, the output of an XOR gate is 1 if either of the two inputs is 1 but not both. Another way to think of this is that the output of an XOR gate is 0 if the two inputs are the same—either both 0 or both 1.
For example, if we close the switches corresponding to A13 and A15, that means we want the memory board to respond to memory addresses A000h through AFFFh. When the address signals A12, A13, A14, and A15 from the bus are equal to the values set on the switches, the outputs of all four XOR gates are 0, which means the output from the NOR gate is 1:
You can then combine that Equal signal with a 2-Line-to-4-Line Decoder to generate signals for each of the four banks of memory:
For example, when A10 is 0 and A11 is 1, that's the third bank.
If you recall the messy details of combining RAM arrays in Chapter 16, you might assume that we also need eight 4-to-1 Selectors to select the correct data output signals from the four banks of memory. But we don't, and here's why.
Normally, the output signals of TTL-compatible integrated circuits are either greater than 2.2 volts (for a logical 1) or less than 0.4 volts (for a logical 0). But what happens if you try connecting outputs? If one integrated circuit has a 1 output and another has a 0 output, and these two outputs are connected, what will result? You can't really tell, and that's why outputs of integrated circuits aren't normally connected together.
The data output signal of the 2102 chip is known as a 3-state, or tri-state, output. Besides a logical 0 and a logical 1, this data output signal can also be a third state. This state is—lo and behold—nothing at all! It's as if nothing is connected to the pin of the chip. The data output signal of the 2102 chip goes into this third state when the input is 1. This means that we can connect the corresponding data output signals of all four banks and use those eight combined outputs as the eight data input signals of the bus.
I'm emphasizing the concept of the tri-state output because it's essential to the operation of a bus. Just about everything that's