Code_ The Hidden Language of Computer Hardware and Software - Charles Petzold [58]
In other words, we want something that has the following function table:
Inputs
Outputs
Data
Hold That Bit
Q
0
1
0
1
1
1
0
0
Q
1
0
Q
In the first two cases, when the Hold That Bit signal is 1, the output Q is the same as the Data input. In the second two cases, when the Hold That Bit signal is 0, the Q output is the same as it was before. Notice in the second two cases that when Hold That Bit is 0, the Q output is the same regardless of what the Data input is. The function table can be simplified a little, like this:
Inputs
Outputs
Data
Hold That Bit
Q
0
1
0
1
1
1
X
0
Q
The X means "don't care." It doesn't matter what the Data input is because if the Hold That Bit input is 0, the output Q is the same as it was before.
Implementing a Hold That Bit signal based on our existing R-S flip-flop requires that we add two AND gates at the input end, as in the diagram at the top of the following page.
Recall that the output of an AND gate is 1 only if both inputs are 1. In this diagram, the Q output is 0 and the output is 1.
As long as the Hold That Bit signal is 0, the Set signal has no effect on the outputs:
Similarly, the Reset signal has no effect:
Only when the Hold That Bit signal is 1 will this circuit function the same way as the normal R-S flip-flop shown earlier:
It behaves like a normal R-S flip-flop because now the output of the upper AND gate is the same as the Reset signal, and the output of the lower AND gate is the same as the Set signal.
But we haven't yet achieved our goal. We want only two inputs, not three. How is this done? If you recall the original function table of the R-S flip-flop, the case in which Set and Reset were both 1 was disallowed, so we want to avoid that. And it doesn't make much sense for the Set and Reset signals to now both be 0 because that's simply the case in which the output didn't change. We can accomplish the same thing in this circuit by setting Hold That Bit to 0.
So it makes sense that if Set is 1, Reset is 0; and if Set is 0, Reset is 1. A signal called Data can be equivalent to a Set, and the Data signal inverted can be the Reset signal:
In this case, both inputs are 0 and the output Q is 0 (which means that is 1). As long as Hold That Bit is 0, the Data input has no effect on the circuit:
But when Hold That Bit is 1, the circuit reflects the value of the Data input:
The Q output is now the same as the Data input, and is the opposite. Now Hold That Bit can go back to being 0:
The circuit now remembers the value of Data when Hold That Bit was last 1, regardless of how Data changes. The Data signal could, for example, go back to 0 with no effect on the output:
This circuit is called a level-triggered D-type flip-flop. The D stands for Data. Level-triggered means that the flip-flop saves the value of the Data input when the Hold That Bit input is at a particular level, in this case 1. (We'll look at an alternative to level-triggered flip-flops shortly.)
Usually when a circuit like this appears in a book, the input isn't labeled Hold That Bit. It's usually labeled Clock. Of course, this signal isn't a real clock, but it might sometimes have clocklike attributes, which means that it might tick back and forth between 0 and 1 on a regular basis. But for now, the Clock input simply indicates when the Data input is to be saved:
And usually when the function table is shown, Data is abbreviated as D and Clock is abbreviated