Code_ The Hidden Language of Computer Hardware and Software - Charles Petzold [61]
The output of the flip-flop is itself an input to the flip-flop. It's feedback upon feedback! (In practice, this could present a problem. The oscillator is constructed out of a relay that's flipping back and forth as fast as it can. The output of the oscillator is connected to the relays that make up the flip-flop. These other relays might not be able to keep up with the speed of the oscillator. To avoid these problems, let's assume that the relay used in the oscillator is much slower than the relays used elsewhere in these circuits.)
To see what happens in this circuit, let's look at a function table that illustrates the various changes. At the start, let's say that the Clock input is 0 and the Q output is 0. That means that the output is 1, which is connected to the D input:
Inputs
Outputs
D
Clk
Q
1
0
0
1
When the Clock input changes from 0 to 1, the Q output will become the same as the D input:
Inputs
Outputs
D
Clk
Q
1
0
0
1
1
↑
1
0
But because the output changes to 0, the D input will also change to 0. The Clock input is now 1:
Inputs
Outputs
D
Clk
Q
1
0
0
1
1
↑
1
0
0
1
1
0
The Clock input changes to back to 0 without affecting the outputs:
Inputs
Outputs
D
Clk
Q
1
0
0
1
1
↑
1
0
0
1
1
0
0
0
1
0
Now the Clock input changes to 1 again. Because the D input is 0, the Q output becomes 0 and the output becomes 1:
Inputs
Outputs
D
Clk
Q
1
0
0
1
1
↑
1
0
0
1
1
0
0
0
1
0
0
↑
0
1
So the D input also becomes 1:
Inputs
Outputs
D
Clk
Q
1
0
0
1
1
↑
1
0
0
1
1
0
0
0
1
0
0
↑
0
1
1
1
0
1
What's happening here can be summed up very simply: Every time the Clock input changes from 0 to 1, the Q output changes, either from 0 to 1 or from 1 to 0. The situation is clearer if we look at the timing diagram:
When the Clock input goes from 0 to 1, the value of D (which is the same as ) is transferred to Q, thus also changing and D for the next transition of the Clock input from 0 to 1.
If the frequency of the oscillator is 20 Hz (which means 20 cycles per second), the frequency of the Q output is half that, or 10 Hz. For this reason, such a circuit—in which the output is routed back to the Data input of a flip-flop—is also known as a frequency divider.
Of course, the output from the frequency divider can be the Clock input of another frequency divider to divide the frequency once again. Here's an arrangement of three of them:
Let's look at the four signals I've labeled at the top of that diagram:
I'll admit that I've started and ended this diagram at an opportune spot, but there's nothing dishonest about it: The circuit will repeat this pattern over and over again. But do you recognize anything familiar about it?
I'll give you a hint. Let's label these signals with 0s and 1s:
Do you see it yet? Try turning the diagram 90 degrees clockwise, and read the 4-bit numbers going across. Each of them corresponds to a decimal number from 0 through 15:
Binary
Decimal
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
10
1011
11
1100
12
1101
13
1110
14
1111
15
Thus, this circuit is doing nothing less than counting in binary numbers, and the more flip-flops we add to the circuit, the higher it will count. I pointed out in Chapter 8 that in a sequence of increasing binary numbers, each column of digits alternates between 0 and 1 at half the frequency of the column to the right. The counter mimics this. At each positive transition of the Clock signal, the outputs of the counter are said to increment, that is, to increase by 1.
Let's string eight flip-flops together and put them in a box:
This is called a ripple counter because the output of each flip-flop becomes the Clock input of the next flip-flop. Changes ripple through the stages sequentially, and the flip-flops at the end might be delayed