Code_ The Hidden Language of Computer Hardware and Software - Charles Petzold [68]
We're halfway finished. Now that we've established what we need for the output side, let's look at the input side.
The input side involves the Data input signals and the Write signal. On the input side of the latches, we can connect all the Data input signals together. But we can't connect the eight Write signals together because we want to be able to write into each latch individually. We have a single Write signal that must be routed to one (and only one) of the latches:
To accomplish this task, we need another circuit that looks somewhat similar to the 8-to-1 Selector but actually does the opposite. This is the 3-to-8 Decoder. We've also seen a simple Data Decoder before—when wiring the switches to select the color of our ideal cat in Chapter 11.
The 3-to-8 Decoder has eight Outputs. At any time, all but one of the Outputs are 0. The exception is the Output that's selected by the S0, S1, and S2 inputs. This Output is the same as the Data Input.
Again, notice that the inputs to the sixth AND gate from the top include S0, 1, S2. No other AND gate has these three inputs. So if the Select inputs are 101, then all the other AND gates will have an output of 0. The sixth AND gate from the top will possibly have an output of 0 if the Data Input is 0 or an output of 1 if the Data Input is 1. Here's the complete logic table:
Inputs Outputs
S2
S1
S0
O7
O6
O5
O4
O4
O2
O1
O0
0
0
0
0
0
0
0
0
0
0
Data
0
0
1
0
0
0
0
0
0
Data
0
0
1
0
0
0
0
0
0
Data
0
0
0
1
1
0
0
0
0
Data
0
0
0
1
0
0
0
0
0
Data
0
0
0
0
1
0
1
0
0
Data
0
0
0
0
0
1
1
0
0
Data
0
0
0
0
0
0
1
1
1
Data
0
0
0
0
0
0
0
And here's the complete circuit with the 8 latches:
Notice that the three Select signals to the Decoder and the Selector are the same and that I've also labeled those three signals the Address. Like a post office box number, this 3-bit address determines which of the eight 1-bit latches is being referenced. On the input side, the Address input determines which latch the Write signal will trigger to store the Data input. On the output side (at the bottom of the figure), the Address input controls the 8-to-1 Selector to select the output of one of the eight latches.
This configuration of latches is sometimes known as read/write memory, but more commonly as random access memory, or RAM (pronounced the same as the animal). This particular RAM configuration stores eight separate 1-bit values. It can be represented this way:
It's called memory because it retains information. It's called read/write memory because you can store a new value in each latch (that is, write the value) and because you can determine what's stored in each latch (that is, you can later read the value). It's called random access memory because each of the eight latches can be read from or written to simply by changing the Address inputs. In contrast, some other types of memory have to be read sequentially—that is, you'd have to read the value stored at address 100 before you could read the value stored at address 101.
A particular configuration of RAM is often referred to as a RAM array. This particular RAM array is organized in a manner called in abbreviated form 8 x 1 (pronounced eight by one). Each of the eight values in the array is 1 bit. Multiply the two values to get the total number of bits that can be stored in the RAM array.
RAM arrays can be combined in various ways. For example, you can take two 8 x 1 RAM arrays and arrange them so that they are addressed in the same way:
The Address and Write inputs of the two 8 x 1 RAM arrays are connected, so the result is an 8 x 2 RAM array:
This RAM array stores eight values, but each of them is 2 bits in size.
Or the two 8 x 1 RAM arrays can be combined in much the same way that the individual latches were combined—by using