CompTIA A_ Certification All-In-One Exam Guide, Seventh Edition - Michael Meyers [74]
The feature set of the early Pentium CPUs beats at the heart of every subsequent processor. Newer processors have a 64-bit data bus, 32-bit or larger address bus, 32-bit or larger registers, multiple pipelines, and two or three levels of cache. All run at some multiple of the system clock. So, now that you have the scoop on the Pentium, you’re ready to check out subsequent CPU models.
Figure 5-34 Typical mother-board voltage regulators
Original Pentium
The Pentium is not a new chip; it’s been around since 1990, and the last versions of the Pentium chip were discontinued in 1995. The original Pentium was the springboard for the Pentium Pro, probably the most important CPU ever made, and thus it makes sense to start there. The rest of this chapter looks at all of the popular CPUs developed since the Pentium and describes how they’ve built on this legacy CPU (Figure 5-35).
Figure 5-35 An early Pentium
AMD made a competitor to the Pentium called the AMD K5. The AMD K5 was pin-compatible with the Pentium, but to keep Intel from suing them, AMD made the K5 very different on the inside, using a totally new (at least for Intel) method of processing. The AMD K5 had some success, but was rather quickly upstaged by better AMD CPUs.
Pentium Pro
In 1995, Intel released the next generation of CPU, the Pentium Pro, often called the P6. The Pentium Pro was a huge CPU with a distinctive, rectangular PGA package (Figure 5-36). The P6 had the same bus and register sizes as the Pentium, but three new items made the P6 more powerful than its predecessor: quad pipelining, dynamic processing, and an on-chip L2 cache. These features carried on into every CPU version that followed, so many people consider the Pentium Pro to be the true “Father of the Modern CPU.”
Figure 5-36 Pentium Pro
Superscalar Execution
The P6 had four pipelines, twice as many as the Pentium. These pipelines were deeper and faster. With this many pipelines, the P6 was guaranteed to always, no matter what, run at least two instructions at the same time. The ability to execute more than one instruction in any one clock cycle is called superscalar execution.
Out-of-Order Processing/Speculative Execution
From time to time, a CPU must go to system memory to access code, no matter how good its cache. When a RAM access takes place, the CPU must wait a few clock cycles before processing. Sometimes the wait can be 10 or 20 clock cycles. System memory is dynamic RAM and needs to be refreshed (charged up) periodically, causing further delays. When the P6 was forced into wait states, it took advantage of the wait to look at the code in the pipeline to see if it could run any commands while the wait states were active. If it found commands it could process that were not dependent on the data being fetched from DRAM, it ran these commands out of order, a feature called out-of-order processing. After the DRAM returned with the code, it rearranged the commands and continued processing.
The P6 improved on the Pentium’s branch prediction by adding a far more complex counter that would predict branches with a better than 90-percent success rate. With the combination of out-of-order processing and the chance of a branch prediction so high, the CPU could grab the predicted side of the branch out of the cache and run it out of order in one pipeline, even before running the branch itself. This was called speculative execution.
On-Chip L2 Cache
The P6 had both an L1 and an L2 cache on the CPU. Because the L2 cache was on the chip, it ran almost as fast as the L1 cache (Figure 5-37). Be careful with the term “on-chip.” Just because the L2 cache was on the chip, that doesn’t mean it was built into the CPU. The CPU and the L2 cache shared the same package, but physically they were separate.
The inclusion of the L2 cache on the chip