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CompTIA A_ Certification All-In-One Exam Guide, Seventh Edition - Michael Meyers [77]

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to make the mask. Most of today’s CPUs are created with a 45-nanometer process, and a 32-nanometer process is appearing in some chips. The same CPU created with a smaller process is usually cooler.

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NOTE A nanometer is one billionth of a meter.

CPU Codenames

Intel and AMD fight to bring out new CPUs with an almost alarming frequency, making the job of documenting all of these CPUs challenging. Luckily for us, the CPU makers use special CPU codenames for new CPUs, such as Bloomfield and Deneb to describe the first version of the Core i7 and the Phenom II X4, respectively. These codenames are in common use, and a good tech should recognize these names—plus they make a dandy way to learn about what’s taking place in the CPU business.

AMD Athlon


Athlon is the brand name for a series of CPUs released by AMD. A number of different CPUs have been launched under this brand to compete head to head against the latest Intel chips. The original Athlon, now referred to as Athlon Classic, was the first AMD CPU to drop any attempt at pin compatibility with Intel chips. Instead, AMD decided to make its own AMD-only slots and sockets. The first of these sockets used an SEC package and was called Slot A (Figure 5-43).

AMD then shifted back to a PGA package with the release of an Athlon CPU code-named Thunderbird (Figure 5-44). This CPU, along with several Athlon CPUs to come, used a proprietary 462-pin socket called Socket A. Thunderbird (like its predecessor) had an interesting double-pumped frontside bus that doubled the data rate without increasing the clock speed. The Athlon Thunderbird CPUs have a smaller but far more powerful L2 cache, as well as a number of other minor improvements when compared to the Athlon Classic.

Figure 5-43 Early Athlon CPU

Figure 5-44 Athlon Thunderbird (photo courtesy of AMD)

Next, AMD launched the Athlon XP, first under the codename Palomino. AMD incorporated a number of performance enhancements to the Athlon core, including support for Intel’s SSE instructions. AMD released an update to Palomino, codenamed Thoroughbred, which featured increased external bus speeds and was manufactured by using a 130-nm process that reduced the required CPU wattage. The last 32-bit CPUs to wear the Athlon badge were codenamed Barton and Thorton. Barton featured double the L2 cache of Thoroughbred and had an even faster external bus. Thorton was a cheaper version that did not increase the size of the cache.

One interesting aspect of the Athlon XP was AMD’s attempt to ignore clock speeds and instead market the CPUs by using a performance rating (PR) number that matched the equivalent power of an Intel Pentium 4 processor. For example, the Athlon XP 1800+ actually ran at 1.6 GHz, but AMD claimed it processed as fast as or faster than a Pentium 4 1.8 GHz—ergo “1800+.”

AMD Duron


Duron is the generic name given to lower-end CPUs based on the Athlon processor. A Duron is basically an Athlon with a smaller cache. Because the Duron supported the same frontside bus as the Athlon, it had a slight performance edge over its low-end rival from Intel at the time. The Duron connected to the same 462-pin Socket A as the later Athlon CPUs (Figure 5-45). AMD discontinued the Duron brand in 2004 and replaced it with the Sempron brand, discussed later in this chapter.

Figure 5-45 AMD Duron (photo courtesy of AMD)

Intel Pentium 4

Although the Pentium II and III were little more than improvements on the Intel Pentium Pro, the Pentium 4 introduced a completely redesigned core, called NetBurst. NetBurst centered around a totally new 20-stage pipeline combined with features to support this huge pipeline. Each stage of the pipeline performed fewer operations than typical pipeline stages in earlier processors, allowing Intel to crank up the clock speed for the Pentium 4 CPUs. The first Pentium 4s, codenamed Willamette, included a new version of SSE called SSE2, and later versions introduced SSE3.

The Pentium 4 featured a quad-pumped frontside bus where the external data bus was sampled four

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