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RAM responds to electrical signals at varying rates. When the memory controller starts to grab a line of memory, for example, a slight delay occurs; think of it as the RAM getting off the couch. After the RAM sends out the requested line of memory, there’s another slight delay before the memory controller can ask for another line—the RAM sat back down. The delay in RAM’s response time is called its latency. RAM with a lower latency—such as CL2—is faster than RAM with a higher latency—such as CL3—because it responds more quickly. The CL refers to clock cycle delays. The 2 means that the memory delays two clock cycles before delivering the requested data; the 3 means a three-cycle delay.

Figure 6-19 Why is one more expensive than the other?

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NOTE Latency numbers reflect how many clicks of the system clock it takes before the RAM responds. If you speed up the system clock, say from 166 MHz to 200 MHz, the same stick of RAM might take an extra click before it can respond. When you take RAM out of an older system and put it into a newer one, you might get a seemingly dead PC, even though the RAM fits in the DIMM slot. Many motherboards enable you to adjust the RAM timings manually. If so, try raising the latency to give the slower RAM time to respond. See Chapter 7, “BIOS and CMOS,” to learn how to make these adjustments (and how to recover if you make a mistake).

From a tech’s standpoint, you need to get the proper RAM for the system you’re working on. If you put a high-latency stick in a motherboard set up for a low-latency stick, you’ll get an unstable or completely dead PC. Check the motherboard manual and get the quickest RAM the motherboard can handle, and you should be fine.

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NOTE CAS stands for column array strobe, one of the wires (along with the row array strobe) in the RAM that helps the memory controller find a particular bit of memory. Each of these wires requires electricity to charge up before it can do its job. This is one of the aspects of latency.

Parity and ECC

Given the high speeds and phenomenal amount of data moved by the typical DRAM chip, a RAM chip might occasionally give bad data to the memory controller. This doesn’t necessarily mean that the RAM has gone bad. It could be a hiccup caused by some unknown event that makes a good DRAM chip say a bit is a zero when it’s really a one. In most cases you won’t even notice when such a rare event happens. In some environments, however, even these rare events are intolerable. A bank server handling thousands of online transactions per second, for example, can’t risk even the smallest error. These important computers need a more robust, fault-resistant RAM.

The first type of error-detecting RAM was known as parity RAM (Figure 6-20). Parity RAM stored an extra bit of data (called the parity bit) that the MCC used to verify whether the data was correct. Parity wasn’t perfect it wouldn’t always detect an error, and if the MCC did find an error, it couldn’t correct the error. For years, parity was the only available way to tell if the RAM made a mistake.

Figure 6-20 Ancient parity RAM stick

Today’s PCs that need to watch for RAM errors use a special type of RAM called error correction code RAM (ECC RAM). ECC is a major advance in error checking on DRAM. First, ECC detects any time a single bit is incorrect. Second, ECC fixes these errors on the fly. The checking and fixing come at a price, however, as ECC RAM is always slower than non-ECC RAM.

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NOTE Some memory manufacturers call the technology Error Checking and Correction (ECC). Don’t be thrown off if you see the phrase—it’s the same thing, just a different marketing slant for error correction code.

ECC DRAM comes in every DIMM package type and can lead to some odd-sounding numbers. You can find DDR2 or DDR3 RAM sticks, for example, that come in 240-pin, 72-bit versions. Similarly, you’ll see 200-pin, 72-bit SO-DIMM format. The extra 8 bits beyond the