CompTIA A_ Certification All-In-One Exam Guide, Seventh Edition - Michael Meyers [71]
1. Fetch Get the data from the EDB.
2. Decode Figure out what type of command needs to be done.
3. Execute Perform the calculation.
4. Write Send the data back onto the EDB.
Smart, discrete circuits inside your CPU handle each of these stages. In early CPUs, when a command was placed on the EDB, each stage did its job and the CPU handed back the answer before starting the next command, requiring at least four clock cycles to process a command. In every clock cycle, three of the four circuits sat idle. Today, the circuits are organized in a conveyer-belt fashion called a pipeline. With pipelining, each stage does its job with each clock-cycle pulse, creating a much more efficient process. The CPU has multiple circuits doing multiple jobs, so let’s add pipelining to the Man in the Box analogy. Now, it’s Men in the Box (Figure 5-27)!
Figure 5-27 Simple pipeline
Pipelines keep every stage of the processor busy on every click of the clock, making a CPU run more efficiently without increasing the clock speed. Note that at this point, the CPU has four stages: fetch, decode, execute, and write—a four-stage pipeline. No CPU ever made has fewer than four stages, but advancements in caching have increased the number of stages over the years. Current CPU pipelines contain many more stages, up to 20 in some cases.
Pipelining isn’t perfect. Sometimes a stage hits a complex command that requires more than one clock cycle, forcing the pipeline to stop. Your CPU tries to avoid these stops, called pipeline stalls. The decode stage tends to cause the most pipeline stalls; certain commands are complex and therefore harder to decode than other commands. The Pentium used two decode stages to reduce the chance of pipeline stalls due to complex decoding.
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NOTE After the Pentium, pipelines kept getting longer, reaching up to 20 stages in the Pentium 4. Since then, Intel and AMD have kept CPU pipelines around 12 stages (although this could change again).
Pipelining certainly helped the Pentium run more efficiently, but there’s another issue: the execute stage. The inside of the CPU is composed of multiple chunks of circuitry to handle the many types of calculations your PC needs to do. For example, one part, the integer unit, handles integer math: basic math for numbers with no decimal point. A perfect example of integer math is 2 + 3 = 5. The typical CPU spends more than 90 percent of its work doing integer math. But the Pentium also had special circuitry to handle complex numbers, called the floating point unit (FPU). With a single pipeline, only the integer unit or the floating point unit worked at any execution stage. Worse yet, floating point calculation often took many, many clock cycles to execute, forcing the CPU to stall the pipeline until the floating point finished executing the complex command (Figure 5-28).
Figure 5-28 Bored integer unit
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NOTE You’ll see the integer unit referred to as the arithmetic logic unit (ALU) in many sources. Either term works.
To keep things moving, the folks at Intel gave the Pentium two pipelines: one main, do-everything pipeline and one that only handled integer math. Although this didn’t stop pipeline stalls, a second pipeline kept running when the main one stalled (see Figure 5-29).
The two pipelines on the old Pentium were so successful that Intel and AMD added more and more pipelines to subsequent CPUs. Most CPUs today have around eight pipelines, although there’s tremendous variance from CPU to CPU.
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NOTE One of the biggest differences between equivalent AMD and Intel processors is the pipelines. AMD tends to go for lots of short pipelines, whereas Intel tends to go with just a few long pipelines.
CPU Cache
When you send a program to the CPU, you actually run