CompTIA A_ Certification All-In-One Exam Guide, Seventh Edition - Michael Meyers [72]
Figure 5-29 The Pentium dual pipeline
Take a look at Figure 5-30. It shows four programs in RAM: a Web browser, Solitaire, an image-editing program, and an e-mail program. Note they are not the same size. Some programs need more RAM than others.
Modern CPUs don’t execute instructions sequentially, first doing step 1, then step 2, and so on; but rather process all kinds of instructions. Most applications have certain instructions and data that get reused, sometimes many times.
Pipelining CPUs work fantastically well as long as the pipelines stay filled with instructions. Because the CPU runs faster than the RAM can supply it with code, you’ll always get pipeline stalls—called wait states—because the RAM can’t keep up with the CPU. To reduce wait states, the Pentium came with built-in, very high-speed RAM called static RAM (SRAM). This SRAM would preload as many instructions as possible and would also keep copies of already run instructions and data in the hope that the CPU would need to work on them again (see Figure 5-31). SRAM used in this fashion is called a cache.
The SRAM cache inside the CPU was tiny, only about 16 KB, but it improved performance tremendously. In fact, it helped so much that many motherboard makers began adding a cache directly to the Pentium motherboards. These caches were much larger, usually around 128 to 512 KB. When the CPU looked for a line of code, it first went to the built-in cache; if the code wasn’t there, the CPU went to the cache on the motherboard. The cache on the CPU was called the L1 cache because it was the one the CPU first tried to use. The cache on the motherboard was called the L2 cache, not because it was on the motherboard but because it was the second cache the CPU checked. Later, engineers took this cache concept even further and added the L2 cache onboard the CPU. Some CPUs even include three caches: an L1, an L2, and an L3 cache.
Figure 5-30 Four programs in RAM
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NOTE You’ll hear caches referred to as Level 1, Level 2, and Level 3 for L1, L2, and L3 cache, respectively. Any of the terms are acceptable.
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NOTE It’s tempting to ask why processor manufacturers didn’t just include bigger L1 caches instead of making onboard L1 and L2 caches. The answer is that a very small L1 and a larger L2 are much more efficient than a single fast L1.
The Pentium was capable of branch prediction, a process whereby the CPU attempted to anticipate program branches before they got to the CPU itself. An IF statement provides a nice example of this: “If the value in the AX register = 5, stop running this code and jump to another memory location.” Such a jump would make all of the data in the cache useless. The Pentium could recognize a branch statement. Using a counter that kept a record about the direction of the previous branch, the CPU would guess which way the branch was going to go and make sure that side of the branch was in its cache. The counter wasn’t perfect, but it was right more often than it was wrong.
Figure 5-31 RAM cache
Clock Speed and Multipliers
In the earliest motherboards, the clock chip pushed every chip on the motherboard, not just the CPU. This setup worked great for a while until it became obvious that CPU makers (really Intel) could make CPUs with a much higher clock speed than the rest of the chips on the motherboard. So Intel had a choice: Either stop making faster CPUs or come up with some way to make CPUs run faster than the rest of the computer.
To overcome this problem, Intel developed clock-multiplying CPUs. A clock- multiplying CPU takes the incoming clock signal and multiplies