Electronics Made Easy - a Complete Introduction to Electronics - Martin Denny [14]
The time delay can be calculated by assuming that T = 1.5CR approximately.
The 555 as an Monostable Multivibrator.
A monostable multivibrator requires a trigger pulse to generate an output pulse. The output waveform will have an equal mark to space ratio.
As before the input network ensures that the trigger pulse is a negative going pulse into pin 2. Reset pin 4 is connected to logic 1 to enable the 555. The output waveform is generated by connecting pin 6 to the input at pin 2 with a suitable capacitor, see figure 10.
The 555 as an Astable or Free Running Multivibrator.
The 555 operating in this mode acts as a free running square wave oscillator where T is approximately 0.25CR for values of R between 1K5W and 6K8W, see figure 11.
This circuit does not always produce an even mark to space ratio, the M-S ratio changes with the values of C and R.
USEFUL LOGIC CIRCUITS
The Latch
The latch retains a logic state until reset. Two examples are shown in figure 12.
For a NAND latch, if A goes from 1 to 0, then Z1 = 1 and Z2 = 0. Z2 holds Z1 at 1 until the latch is reset ie R goes to 0.
For a NOR latch, if A goes to 1, then Z1 = 0, and Z2 = 1. Z2 holds Z1 at 0 until reset R goes to 1.
Inhibit
The operation of a gate can be disabled or blocked by controlling one of the inputs, see figure 13.
Figure 13 shows two examples, although this technique can be used for all logic gates. For NAND the output of gate 1 will only change state with input A when the inhibit input I is at logic 1. Gate 2 is connected as an invertor. A = Z when I = logic 1.
For NOR the output of gate 1 with input A when the inhibit input I is at logic 0. Gate 2 is connected as an invertor. A = Z when I = logic 0.
Time Delay
A time delay can be incorporated in a logic design by the addition of a resistor and capacitor in a logic circuit as shown in figure 14. Similarly a solid logic 1 can be converted into a pulse by feeding the signal into a series capacitor and discharging through a resistor.
When the output of invertor 1 goes high capacitor C is charged via resistor R. The voltage across C rises until it reaches logic 1, and the output of invertor 2 goes to 0. The minimum value of logic 1 for CMOS is 0.7Vs, for TTL 2v at a nominal supply voltage of 5v.
To calculate time delay:
T = 0.7CR for CMOS T = 0.4CR for TTL
The pulse width control circuit shown in figure 4 could equally be described as a timer. If a continuous logic 1 is used as a trigger, ie reset after timing period then input should be fed via a capacitor and discharge resistor, the value of T being much less than that of the timer.
Astable Multivibrator.
The Astable Multivibrator design shown in figure 15 uses 2 inverting buffers to generate a square wave output. The third invertor provides a buffered output which may not be necessary if the multivibrator is lightly loaded, ie feeding another gate.
Again the pulse width equals 0.7CR so the time between pulses equals 1.4CR, and the frequency F = 1/1.4CR.
DESIGN
The design of any device requires careful attention to detail. It is not simply enough to design an electronic device to perform a specific function but its packaging and ease of operation must have an equal importance.
In determining the viability of a design the first question a customer will ask will be can it be done, if so when and how much will it cost. In practice the first question is irrelevant as virtually any task imaginable can be achieved with unlimited time and money. The second two questions are interrelated, as for a design project to be successful in general there must be a financial advantage in its continued